[rram_ctrl] rram_analog, rram_jtag
Open
- Dominant language
- SystemVerilog
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- 2d 22h
- Merged PRs (30d)
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Description
https://github.com/lowRISC/opentitan/pull/30913#discussion_r3794665906
add test for:
- `RRAM_ANALOG`
- `rram_jtag`
Contributor guide
Research direction
Start with the discussion linked from PR #30913 and inspect the RRAM_ANALOG and rram_jtag entry points. Add tests covering both named targets, then verify that the tests pass and exercise the expected behavior.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 55/100