[rram_ctrl] host side unittest
Open
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Add `rram_ctrl_unittest.cc` and use `mock_rram_ctrl` in other unittests.
This is related to https://github.com/lowRISC/opentitan/pull/30424
Contributor guide
Research direction
Start by reviewing the related pull request and the existing rram_ctrl code and unittest patterns. Add rram_ctrl_unittest.cc, then update the other unittests to use mock_rram_ctrl; done means the new and affected unittests build and pass.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- cpp
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 65/100