[ci,fpga] Re-enable SW build of flaky FPGA manuf tests
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- Dominant language
- SystemVerilog
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- 2d 22h
- Merged PRs (30d)
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Description
PR #30912 disables a set of unstable and flaky manufacturing tests entirely to increase the stability of the CI. Currently the tests are completely disabled.
Even if we cannot run the tests currently in CI, they should still be built to ensure we at least have no non-functional regression.
Once the underlying issue has been identified and fixed, these tests will be re-enabled (#30922).
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Review PR #30912 to identify how the FPGA manufacturing tests were disabled and find the related CI build configuration. Confirm that the tests remain excluded from execution but are included in the software build, then verify the CI build succeeds. Track #30922 for the later re-enablement work.
Written by the indexing model from the issue text.
Assessment
- Domain
- build-system, ci-cd, testing
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100