[sw,rram_ctrl] add tests for dif_rram_ctrl
Open
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
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- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
- [ ] add untitests
- [ ] extend with more functionality such as errors
Contributor guide
Research direction
Start by locating the dif_rram_ctrl entry point and nearby unit-test conventions. Define the test scope for dif_rram_ctrl, including error behavior, and consider the work complete when unit tests cover the requested functionality and errors.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 38/100