lowRISC / lowRISC/opentitan

[rram_ctrl] ecc tests

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SystemVerilog
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Description

The following tests need to be ported to RRAM.

  • sw/device/silicon_creator/rom_ext/e2e/ownership/BUILD : flash_permission_test_slot_{aa,ab,ba,bb}
  • sw/device/silicon_creator/rom_ext/e2e/flash_ecc_error/BUILD : flash_ecc*_test
  • sw/device/silicon_creator/rom/e2e/boot_policy_flash_ecc_error/BUILD : boot_policy_flash_ecc_error*_test, flash_exc_handler_disabled_test
  • sw/device/silicon_creator/rom/e2e/BUILD : rom_e2e_flash_ctrl_init
  • sw/device/tests/BUILD : four flash_ctrl tests : flash_ctrl_ops_test, flash_ctrl_clock_freqs_test, flash_ctrl_test, flash_ctrl_idle_low_power_test

They have been disabled on earlgrey CI for now.

Contributor guide

Open the contributing guide

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start by reading the listed BUILD entries and the definitions of the ownership, flash ECC, boot policy, flash controller, and ROM end-to-end tests. Determine how each test must be ported to RRAM and why it is disabled on earlgrey CI; done means all listed tests run successfully for RRAM and are no longer disabled there.

Written by the indexing model from the issue text.

Assessment

Domain
build-system, embedded-iot, testing
Issue type
Refactor
Difficulty
4/5
Estimated time
3-5 days
Activity status
Quiet
Clarity
Mostly clear
Newbie friendliness
45/100

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