[rram_ctrl,sw] constant runtime for crypto functions
- Dominant language
- SystemVerilog
- Stars
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- Avg merge
- 2d 22h
- Merged PRs (30d)
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Description
The following tests expect a constant runtime for sub functions (e.g. hardened_xor). This cannot be guaranteed if we fetch instructions from the RRAM.
```
//sw/device/lib/base:hardened_memory_functest_fpga_cw340_sival_rom_ext
//sw/device/tests/crypto:aes_gcm_timing_functest_fpga_cw340_sival_rom_ext
//sw/device/lib/base:hardened_memory_functest_fpga_cw340_rom_with_fake_keys
//sw/device/tests/crypto:aes_gcm_timing_functest_fpga_cw340_rom_with_fake_keys
```
The read-time is not constant due to:
- double read from RRAM with verification read that can stall instruction fetch if the read-buffer is full
- not guaranteed read latency
Contributor guide
Research direction
Start with the four affected test targets listed in the issue, especially the hardened memory and AES-GCM timing tests. Read how they measure or assert constant runtime, then compare those expectations with the documented RRAM double-read and variable-latency behavior. Done means the affected tests account for the stated hardware timing constraints and pass.
Written by the indexing model from the issue text.
Assessment
- Domain
- cryptography, embedded-iot, security, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 38/100