[spi_device] Implement an end-of-transfer interrupt

Nobody has claimed this yet.

### Description

#29623 requests the ability for Device SW to be notified via interrupt when an emulated spi_flash transfer completes. This would be desirable for end-of-reads from the Flash Payload Buffer particularly.

Implement a new interrupt which asserts upon end of transfer. This should be a standard event-type CIP interrupt.

Without qualification, this interrupt has the potential to be quite noisy and difficult to handle from a software perspective without careful enabling/masking. A host polling the BUSY bit to await the completion of a non-trivial operation is a canonical example. A hardware mechanism to qualify the interrupt assertion should be considered alongside its implementation if it can be done cheaply and reliably. Options initially discussed have been a read address comparator (similar to LAST_READ_ADDR but an event-based gate on seeing the read touch a certain address), or a command/opcode comparator (allowing the received command or message type of the transfer to be an enabling factor for interrupt assertion). This should be investigated as part of the implementation work.

The software implications for such a feature should be well articulated in the documentation as part of the design. Software will likely need to query the block's registers to understand the context of the end-of-message interrupt, and we should ensure that it is clear what conclusions software can or cannot safely draw about the state of the link based upon receiving this interrupt.

Start by tracing the SPI device's BUSY and LAST_READ_ADDR behavior and its existing register and CIP interrupt conventions. Investigate the proposed address- or command-based qualification options, then document the software-visible context and safe conclusions after the end-of-transfer interrupt. Done means the interrupt behavior, qualification mechanism, and software implications are defined and implemented.

Written by the indexing model from the issue text.