lowRISC / lowRISC/opentitan

[bazel,opentitanlib] Autogenerate rust bindings for an FPGA bkdr_loader IP header

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Component:Software
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SystemVerilog
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Description

### Description

For most IPs, we have an ["ot_hal" which is generated for Rust using Bindgen](https://github.com/lowRISC/opentitan/blob/master/sw/host/ot_hal/bindgen/BUILD), which will automatically generate relevant constants for using various registers / fields and other parameters. This is not available for the FPGA-specific bkdr_loader IP, which is not registered in the standard way through IPGen, and is instead included only in the CW340 top-level and in the Xilinx primitives.

This means that the host-side software implementation in OpenTitanLib instead needs to [manually define these constants](https://github.com/lowRISC/opentitan/blob/84f528505abe923cb404920e7bb0283ab6ff97ae/sw/host/opentitanlib/src/io/fpga_backdoor.rs#L18). As a bit of cleanup, it would be nice to automatically generate a header for the bkdr_loader IP as we do for the other blocks (via Bazel), and simply use it from this rust module.

Contributor guide

Open the contributing guide

Research direction

Inspect sw/host/ot_hal/bindgen/BUILD and sw/host/opentitanlib/src/io/fpga_backdoor.rs, along with the bkdr_loader IP header and existing Bindgen generation path. Follow how other IPs are generated through Bazel. Done when Rust bindings for the FPGA-specific bkdr_loader are generated and fpga_backdoor.rs uses them instead of manually defined constants.

Written by the indexing model from the issue text.

Assessment

Tech stack
rust
Domain
build-system
Issue type
Refactor
Difficulty
3/5
Estimated time
1-2 days
Activity status
Quiet
Clarity
Mostly clear
Newbie friendliness
68/100

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