[test-triage]
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- SystemVerilog
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Description
### Hierarchy of regression failure
Block level
### Failure Description
How can i run all failed cases at once using opentitan in my tb
### Steps to Reproduce
- GitHub Revision: HASH_VALUE
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
$ dvsim hw/top_earlgrey/dv/chip_sim_cfg.hjson -i TEST_NAME --build-seed BUILD_SEED --fixed-seed FAILING_SEED --waves fsdb
- Kokoro build number if applicable
### Tests with similar or related failures
- [ ] Test_name_1
- [ ] Test_name_2
Contributor guide
Research direction
Start with the OpenTitan regression command shown in the issue, hw/top_earlgrey/dv/chip_sim_cfg.hjson, and the dvsim invocation fields. Determine how failed cases are identified and whether the requested batch run can be reproduced from the supplied command. Done means the procedure for running all failed cases at once is clear and reproducible.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100