lowRISC / lowRISC/opentitan

[keymgr_dpe, test] Implement missing `chip_sw_keymgr_dpe_sideload_otbn_vseq.sv`

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#30,689 0 comments 0 reactions 1 assignee View on GitHub

@rroth-lowrisc is already working on this.

Since Jul 8, 2026.

Component:DV IP:keymgr_dpe
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SystemVerilog
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Description

Description

Should this vseq be implemented? On all the other offload ports (kmac, aes) the corresponding vseq verifies the operation. However the chip_sw_keymgr_dpe_sideload_otbn_vseq.sv is missing any verification.

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