lowRISC / lowRISC/opentitan

[kmac,rtl] Bogus CmdSparse_M assertion

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Component:RTL IP:kmac
Dominant language
SystemVerilog
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Description

### Description

In `kmac.sv` is an assertion (an assumption actually) about the possible behaviour of software. The assertion is:
```systemverilog
// Command input should be sparse
`ASSUME(CmdSparse_M, reg2hw.cmd.cmd.qe |-> reg2hw.cmd.cmd.q inside {CmdStart, CmdProcess,
CmdManualRun,CmdDone, CmdNone})
```

Since the field uses `prim_subreg_ext`, this is actually saying that when a TL transaction tries to write to the register, the field's portion of the wdata is one of five special 6-bit values.

This isn't really something that belongs in design RTL... I managed to trigger the assertion failure when porting some of this code to the Caliptra project. The reason that we hadn't seen it in OpenTitan is that the `csr_rw` test is constrained not to write to the `CMD` register.

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