lowRISC / lowRISC/opentitan

[keymgr_dpe, rtl] Reset REGWEN when (initally) loading the UDS

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#30,666 0 comments 0 reactions 1 assignee Claimed by @rroth-lowrisc View on GitHub
Component:RTL IP:keymgr_dpe
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SystemVerilog
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Description

### Description

Currently the REGWEN registers ([**MaxKeyVersion**](https://opentitan.org/book/hw/ip/keymgr_dpe/doc/registers.html#max_key_ver_regwen), [**SW binding register**](https://opentitan.org/book/hw/ip/keymgr_dpe/doc/registers.html#sw_binding_regwen), [**SlotPolicy**](https://opentitan.org/book/hw/ip/keymgr_dpe/doc/registers.html#slot_policy_regwen)) are not unlocked after the initial advancement (which loads the UDS into the selected slot). However, when loading the UDS into the selected slot, the RTL copies the MaxKeyVersion [from the SW register](https://github.com/lowRISC/opentitan/blob/98a020b74d02c316fc2cc682bb212214b5c27e0e/hw/ip/keymgr_dpe/rtl/keymgr_dpe_ctrl.sv#L312). Due to the missing unlock signal this register is never reset and locked until the next advance call.

This can be either fixed by two ways:
- Set a _UDS_DEFAULT_MAX_KEY_VERSION_ like done with the [DEFAULT_POLICY](https://github.com/lowRISC/opentitan/blob/98a020b74d02c316fc2cc682bb212214b5c27e0e/hw/ip/keymgr_dpe/rtl/keymgr_dpe_pkg.sv#L115) but then it would be fixed for all user.
- Set the unlock signal to high if the UDS is loaded (preferred)

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