[CHERIoT] Add constraint logic for legal capability operand generation: for any instruction requiring a valid capability source, constrain the chosen register to one the tracker marks as tagged, in-bounds, and with the required permission bits set.
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- SystemVerilog
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Description
This issue has no description.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No file, test, or entry point is named. Start by locating the CHERIoT legal capability operand generation logic and the register tracker it consults; then determine where constraints are applied. Done means every instruction requiring a valid capability source selects only a tagged, in-bounds register with the required permission bits.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, security
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100