[CHERIoT] Modify behavior of existing instructions that work differently under CHERIoT (control flow, memory access, address construction)
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- Dominant language
- SystemVerilog
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Description
This issue has no description.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue body names no files, tests, or entry points. Clarify which CHERIoT instruction behaviors are affected and what completed changes should cover before starting.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100