[CHERIoT] Post-silicon (SiVal) tests (porting to FPGA/ASIC and debugging)
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- Dominant language
- SystemVerilog
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Description
This issue has no description.
Contributor guide
Research direction
The issue has no body, file references, test names, or entry points to follow. Start by locating the CHERIoT SiVal tests and their FPGA/ASIC porting documentation, then clarify the target platform, debugging scope, and acceptance criteria before beginning.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100