[CHERIoT] Bus changes
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- Dominant language
- SystemVerilog
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Description
This issue has no description.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue provides no files, tests, entry points, or implementation details. Clarify which bus changes are required and define acceptance criteria before identifying the affected OpenTitan components and verification needed to consider the work complete.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 15/100