[CHERIoT] RTL implementation of the CHERIoT memory subsystem

@SamuelRiedel is already working on this.

Since Sep 14, 2026.

## Merge Steps for CHERIoT memory subsystem
### Ibex
* [x] Add TRVK to Ibex: lowRISC/ibex#2455
* [x] Integrate TRVK into Ibex top: lowRISC/ibex#2456

### OpenTitan
* [x] Vendor Ibex (and common_cells) into OpenTitan: #30538
* [x] Point vendored Ibex to `lowRISC/ibex`
* [x] Add CHERIoT interconnect IPs to OpenTitan: #30539
* [x] Add CHERIoT integrate switch IP in `rv_core_ibex`: #30540
* [x] Integrate CHERIoT interconnect IPs into OpenTitan: #30541

## OpenTitan WG / TC
* [x] Prepare RFCs
* [x] Present RFCs
* [x] Get RFCs accepted

## Implementation
* [ ] Add optional cuts between the meta store and the filter blocks after running physical synthesis to evaluate the timing of the extended memory system
* [ ] Handle peripherals with bit-granular access (GPIO, PLIC). #30491

## Security
* [x] Connect all alerts and errors
* [ ] Lockstep TRVK in Ibex
* [ ] Lockstep TRVK revocation bitmap TL translation in `rv_core_ibex`
* [ ] Switch to a MuBi4 for capability tags between `rv_core_ibex` and CHERIoT subsystem
* [ ] Lockstep CHERIoT interconnect subsystem
* [ ] Re-enable scrambling in meta SRAM (non-power of two)

## Open Questions
* [ ] Is missing capability-aware SBA detrimental to debug performance?
* [ ] How is debug module extended to be capability-aware? Are there tag connections required between Ibex and the DM?