lowRISC / lowRISC/opentitan

[rom/rom_ext] Current strength and slew rate should be configurable from ROM/ROM_EXT stage

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#30,361 1 comment 0 reactions 0 assignees View on GitHub
SW:ROM SW:ROM_EXT Triage Priority
Dominant language
SystemVerilog
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Description

### Description

Recommend to make pin strength and slew rate configurable at `ROM` and `ROM_EXT` level:

* Allocate OTP words to store the pin configuration for interfaces used in the ROM (e.g. `SPI_DEV`)
* Support pin default settings in ownership config and/or based on `SW_STRAP` settings.

Contributor guide

Open the contributing guide

Research direction

Start by tracing the ROM and ROM_EXT entry points that configure interfaces such as SPI_DEV, then review how OTP words, ownership config, and SW_STRAP settings are represented. Done means defining and implementing a clear way for ROM-stage pin strength and slew rate defaults to be configured through the proposed sources.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, security
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Active
Clarity
Mostly clear
Newbie friendliness
35/100

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