lowRISC / lowRISC/opentitan

[otbn] Add support for pseudo-instructions in the assembler

Open
#2,967 5 comments 0 reactions 0 assignees View on GitHub
Component:Tooling Earlgrey-PROD Candidate IP:otbn Priority:P4 Type:Enhancement Type:FutureRelease
Dominant language
SystemVerilog
Stars
3.6k
Forks
1.1k
Avg merge
2d 22h
Merged PRs (30d)
141

Description

To do so, we should add some more instructions into `insns.yml`. These don't get an encoding but instead have a rule for generating a sequence of real instructions.

Currently on the list:

- [x] `nop`
- [x] `li`: This can be expressed as LUI; ADDI, but is a bit difficult because ADDI takes a signed immediate. So "constant materialisation" needs to get there by subtraction in some cases. Not sure how to do that in the YAML: maybe we have a "there's some Python code for this!" escape hatch?
- [x] `ret`
- [ ] `loop / endloop`

Contributor guide

Open the contributing guide

Research direction

Start with insns.yml and the existing nop, li, and ret pseudo-instruction entries to understand how assembler expansion rules are represented. Trace the assembler path that consumes these entries, then determine the required loop/endloop expansion and verify that both pseudo-instructions assemble into the intended real-instruction sequences.

Written by the indexing model from the issue text.

Assessment

Tech stack
python
Domain
compilers
Issue type
Feature
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.