lowRISC / lowRISC/opentitan

[spi_host] SPI / QSPI direct mapped mode

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Description

### Description

Hi,

I am going through the SPI Host peripheral, and I am not able to find if SPI/QSPI Host does support
"direct mapped operation". I mean something like:
1. Configure in registers which QSPI command code corresponds to read / write.
2. Incoming Read / Write TL-UL transfers to a certain memory region would then automatically translate to QSPI transfers.

This is useful use-case on how to get XIP or directly mapped external SRAM/PSRAM.

Is such mode available, I can't seem to find this in docs. If not, is this planned / of interest, or is
it avoided for e.g. security reasons ?

Thanks in advance for reply

Contributor guide

Open the contributing guide

Research direction

Start with the SPI Host documentation and register descriptions, then check how SPI/QSPI commands and incoming TL-UL transfers are currently specified. The issue is complete only when direct-mapped operation is either documented as supported or its feasibility and intended direction are decided.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Quiet
Clarity
Needs clarification
Newbie friendliness
25/100

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