[ci] Inconsistent CI gates
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@AlexJones0 is already working on this.
Since Feb 17, 2026.
Component:CI
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Description
### Description
If a new contributor opens a PR, there is a gate that stops quick lint, the merge blocker, and a post-FPGA-job check unless a committer approves the CI job.
Some sort of gating is reasonable, but our configuration doesn't currently gate the block-level and chip-level DV tests or AscentLint.
This seems a little strange: I would have thought that quick lint (which takes a few minutes to fail) is more sensible to run unconditionally than something that takes the best part of an hour with multiple cores.
We should probably revisit this (and possible document it too).
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