lowRISC / lowRISC/opentitan

[ECC] How could I use secded_gen.py script only?

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SystemVerilog
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Description

### Description

Hi,
I currently need to implement ECC scripting for verifying data of arbitrary bit width. How should I extract the ECC scripting-related components from the entire project?

Contributor guide

Open the contributing guide

Research direction

Start by locating secded_gen.py and reading its command-line entry point and nearby ECC documentation or tests. Determine the supported way to run the script independently, including inputs and outputs for arbitrary bit widths; done means a documented, reproducible invocation.

Written by the indexing model from the issue text.

Assessment

Tech stack
python
Domain
tooling
Issue type
Documentation
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
30/100

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