[earlgrey,otp,bazel] OTP build fails with "invalid OTP address" after modifying top_earlgrey

Description

I am currently trying to run Earlgrey on an FPGA platform (KC705). Since KC705 cannot support the full Earlgrey configuration, I removed several peripheral modules, including:

spi_dev

spi_host1

usb_dev

uart1–3

i2c1–2

After running topgen.py, I noticed that the size of
OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION in otp_ctrl.hjson was reduced from 80 to 56.

When I try to rebuild the OTP images using:

bazel build hw/top_earlgrey/data/otp:img_rma

in order to generate:

test_rom_fpga_cw310.32.vmem

otp_img_fpga_cw310.vmem

the build fails with the following error:

invalid OTP address OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION + 0x0000e0

It seems that after removing some IPs, the OTP address map is no longer consistent with what opentitantool expects.

What would be the correct way to fix this issue?
Should I:

regenerate or adjust the OTP layout manually,

update the alert classification configuration,

or modify the related OTP / topgen configuration so that the address map remains valid for a reduced Earlgrey configuration?

Any guidance on the proper approach to resolve this mismatch would be appreciated.

Start with otp_ctrl.hjson, the OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION entry, and the topgen.py output; reproduce the failure with bazel build hw/top_earlgrey/data/otp:img_rma. Trace how the reduced configuration changes the OTP address map and how opentitantool validates it. Done means the reduced Earlgrey OTP images build without the invalid-address error and the generated addresses remain consistent.