[alert,dv] Model variable signal skew in chip-level testbench
- Dominant language
- SystemVerilog
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- 2d 22h
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Description
Currently the skew for alerts is fixed, as defined by RTL and constraints, for all alerts internal to OpenTitan.
For alerts coming in from external, the skew is not fully under OpenTitan control. To support this, we have introduced the `SkewCycles` parameter, which defines the maximum number of skew cycles (i.e., a skew of the differential alert signals between 0 and `SkewCycles` is legal, a larger skew is a violation of the protocol, which leads an alert itself). We don't currently _test_ this, however.
To test this, we would have to add external alerts to a top-level design (probably Darjeeling) and extend the chip-level wrapper used in DV to vary the skew (either constant per run based on seed, or even dynamic over time within one run).
Note that we exercise the skew assertions in FPV but not in DV. This issue is about exercising them in DV, but that may not be highest priority given FPV coverage.
Contributor guide
Research direction
Start by reviewing the chip-level wrapper used in DV, the Darjeeling top-level design, and the existing FPV skew assertions. The work is done when DV exercises external-alert skew within the legal 0-to-SkewCycles range and verifies that larger skew violates the protocol.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100