Various Verilator errors when building (PINMISSING, NEEDTIMINGOPT)

Hi, I did the following steps:

1. Clone the opentitan repo
2. `uv sync` and activate the venv.
3. `bazel build //hw:verilator` (taken from the docs somewhere)

I get a load of warnings and some errors. Is this expected? I'm using `Verilator 5.032 2025-01-01 rev (Debian 5.032-1)`.

Here's a sample (full output was too long for Github Issues):

```
INFO: verilator -f lowrisc_dv_top_earlgrey_chip_verilator_sim_0.1.vc -DDISABLE_PRIM_CDC_RAND_DELAY --trace --trace-fst --trace-structs --trace-params --trace-max-array 1024 --unroll-count 512 -CFLAGS " -std=c++17 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_sim_tb" -LDFLAGS " -pthread -lutil -lelf" -Wall --threads 4 -Wno-fatal --threads 4

ERROR: %Warning-PINMISSING: src/lowrisc_systems_chip_earlgrey_verilator_0.1/rtl/chip_earlgrey_verilator.sv:341:7: Cell has missing pin: 'mux_iob_sel_o'
341 | ast u_ast (
| ^~~~~
src/lowrisc_systems_top_earlgrey_ast_0.1/rtl/ast.sv:127:24: ... Location of port declaration
127 | output logic [4-1:0] mux_iob_sel_o,
| ^~~~~~~~~~~~~
... For warning description see https://verilator.org/warn/PINMISSING?v=5.032
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: src/lowrisc_systems_chip_earlgrey_verilator_0.1/rtl/chip_earlgrey_verilator.sv:501:5: Cell has missing pin: 'obs_ctrl_i'
501 | ) top_earlgrey (
| ^~~~~~~~~~~~
src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:174:40: ... Location of port declaration
174 | input ast_pkg::ast_obs_ctrl_t obs_ctrl_i,
| ^~~~~~~~~~
%Warning-PINMISSING: src/lowrisc_systems_chip_earlgrey_verilator_0.1/rtl/chip_earlgrey_verilator.sv:501:5: Cell has missing pin: 'sram_ctrl_main_cfg_i'
501 | ) top_earlgrey (
| ^~~~~~~~~~~~
src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:176:69: ... Location of port declaration
176 | input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_cfg_i,
| ^~~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: src/lowrisc_systems_chip_earlgrey_verilator_0.1/rtl/chip_earlgrey_verilator.sv:501:5: Cell has missing pin: 'sram_ctrl_ret_aon_cfg_i'
501 | ) top_earlgrey (
| ^~~~~~~~~~~~
src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv:177:71: ... Location of port declaration
177 | input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlRetAonNumRamInst-1:0] sram_ctrl_ret_aon_cfg_i,
| ^~~~~~~~~~~~~~~~~~~~~~~
...
%Warning-WIDTHTRUNC: src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:269:29: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits.
: ... note: In instance 'chip_sim_tb.u_dut.top_earlgrey.u_i2c2.i2c_core.u_i2c_target_fsm'
269 | assign acq_fifo_remainder = AcqFifoDepth - acq_fifo_depth_i;
| ^
%Warning-WIDTHEXPAND: src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:418:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
: ... note: In instance 'chip_sim_tb.u_dut.top_earlgrey.u_i2c2.i2c_core.u_i2c_target_fsm'
418 | if (tcount_q == 20'd1) begin
| ^~
%Warning-WIDTHEXPAND: src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:510:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
: ... note: In instance 'chip_sim_tb.u_dut.top_earlgrey.u_i2c2.i2c_core.u_i2c_target_fsm'
510 | if (tcount_q == 20'd1) begin
| ^~
%Warning-WIDTHEXPAND: src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:720:31: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
: ... note: In instance 'chip_sim_tb.u_dut.top_earlgrey.u_i2c2.i2c_core.u_i2c_target_fsm'
720 | end else if (tcount_q == 20'd1) begin
| ^~
%Warning-WIDTHEXPAND: src/lowrisc_ip_i2c_0.1/rtl/i2c_target_fsm.sv:759:22: Operator EQ expects 20 bits on the LHS, but LHS's VARREF 'tcount_q' generates 16 bits.
: ... note: In instance 'chip_sim_tb.u_dut.top_earlgrey.u_i2c2.i2c_core.u_i2c_target_fsm'
759 | if (tcount_q == 20'd1) begin
| ^~
...
%Error-NEEDTIMINGOPT: src/lowrisc_systems_top_earlgrey_ast_0.1/rtl/vio_pgd.sv:30:22: Use --timing or --no-timing to specify how delays should be handled
: ... note: In instance 'chip_sim_tb.u_dut.u_ast.u_viob_pok'
30 | init_start = 1'b1; #1;
| ^
%Error-NEEDTIMINGOPT: src/lowrisc_systems_top_earlgrey_ast_0.1/rtl/vio_pgd.sv:39:18: Use --timing or --no-timing to specify how timing controls should be handled
: ... note: In instance 'chip_sim_tb.u_dut.u_ast.u_viob_pok'
39 | vio_pok_o <= #(ast_bhv_pkg::VIO_POK_RDLY) gen_supp_a;
| ^
%Error-NEEDTIMINGOPT: src/lowrisc_systems_top_earlgrey_ast_0.1/rtl/vio_pgd.sv:42:18: Use --timing or --no-timing to specify how timing controls should be handled
: ... note: In instance 'chip_sim_tb.u_dut.u_ast.u_viob_pok'
42 | vio_pok_o <= #(ast_bhv_pkg::VIO_POK_FDLY) gen_supp_a;
| ^
%Error-NEEDTIMINGOPT: src/lowrisc_systems_top_earlgrey_ast_0.1/rtl/vcc_pgd.sv:30:22: Use --timing or --no-timing to specify how delays should be handled
: ... note: In instance 'chip_sim_tb.u_dut.u_ast.u_vcc_pok'
30 | init_start = 1'b1; #1;
| ^
%Error-NEEDTIMINGOPT: src/lowrisc_systems_top_earlgrey_ast_0.1/rtl/vcc_pgd.sv:39:18: Use --timing or --no-timing to specify how timing controls should be handled
: ... note: In instance 'chip_sim_tb.u_dut.u_ast.u_vcc_pok'
39 | vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_RDLY) gen_supp_a;
| ^
%Error-NEEDTIMINGOPT: src/lowrisc_systems_top_earlgrey_ast_0.1/rtl/vcc_pgd.sv:42:18: Use --timing or --no-timing to specify how timing controls should be handled
: ... note: In instance 'chip_sim_tb.u_dut.u_ast.u_vcc_pok'
42 | vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_FDLY) gen_supp_a;
| ^
...
%Error: Exiting due to 6 error(s)
make: *** [Makefile:15: Vchip_sim_tb.mk] Error 1
```

Reproduce the failure with `uv sync` followed by `bazel build //hw:verilator`, then inspect the generated Verilator invocation and `Makefile:15`. Review the reported locations in `chip_earlgrey_verilator.sv`, `vio_pgd.sv`, and `vcc_pgd.sv`; done means the documented build completes with Verilator 5.032 or the expected warnings and required options are clearly established.

Written by the indexing model from the issue text.