RFC: Phase-Aligned PWM Disable
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
Hi all,
I’d like to propose making the PWM disable phase-aligned by sampling the software enable only when the PWM is idle. This prevents mid-pulse truncation and preserves the exact duty for the final active cycle, which benefits downstream analog/power stages and multi-channel synchronization.
The full draft RFC (markdown) is here:
https://github.com/EneaDim/flexsoc/blob/main/opentitan_issues/rfc_pwm.md
I outline three approaches—(1) make it the default, or for backwards compatibility (2) enable it via a compile-time parameter, or (3) enable it via a runtime configuration bit. The attached markdown shows the default-behavior variant.
I’d welcome feedback on whether this may become the default versus parameterized/configurable, and any integration concerns.
Best regards,
Enea Dimroci
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the linked draft at opentitan_issues/rfc_pwm.md, focusing on the three proposed approaches and their integration concerns. The issue is ready only after maintainers decide whether phase-aligned disable should be the default or configurable, and define the accepted implementation scope.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100