[build] ERROR: [Updatemem 57-44] xc7k410t device is not supported by update_mem.

Nobody has claimed this yet.

### Description

I think this is still unresolved from https://github.com/lowRISC/opentitan/issues/22707

1. Pulled this branch: git clone https://github.com/lowRISC/opentitan.git -b earlgrey_1.0.0
2. Installed Latest Vivado Lab Edition
3. Build attempt:

```
`INFO: From SpliceBitstream hw/bitstream/universal/splice-rom.bit:
ERROR: [Updatemem 57-44] xc7k410t device is not supported by update_mem.

****** updatemem v2025.1 (64-bit)
**** SW Build 6140146 on Wed May 21 17:37:51 MDT 2025
**** Start of session at: Sat Aug 30 18:44:20 2025
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.

source /tools/Xilinx/2025.1/Vivado_Lab/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo external/+_repo_rules+bitstreams/cache/a3c070fd48a4533a60d5e04df872f020a82298e9/chip_earlgrey_cw310_hyperdebug/memories.mmi -data bazel-out/k8-fastbuild-ST-676f6b5b63bd/bin/hw/bitstream/universal/splice-rom.update.mem -proc rom -bit external/+_repo_rules+bitstreams/cache/a3c070fd48a4533a60d5e04df872f020a82298e9/chip_earlgrey_cw310_hyperdebug/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit -out bazel-out/k8-fastbuild-ST-676f6b5b63bd/bin/hw/bitstream/universal/splice-rom.bit -force
Loading bitfile external/+_repo_rules+bitstreams/cache/a3c070fd48a4533a60d5e04df872f020a82298e9/chip_earlgrey_cw310_hyperdebug/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit
0 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
update_mem failed
update_mem: Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 1051.535 ; gain = 543.160 ; free physical = 771 ; free virtual = 17551
ERROR: [Common 17-39] 'update_mem' failed due to earlier errors.

INFO: [Common 17-206] Exiting updatemem at Sat Aug 30 18:45:06 2025...
ERROR: /User_data/home/irangel/otn/opentitan/hw/bitstream/universal/BUILD:29:17: output 'hw/bitstream/universal/splice-rom.bit' was not created
ERROR: /User_data/home/irangel/otn/opentitan/hw/bitstream/universal/BUILD:29:17: SpliceBitstream hw/bitstream/universal/splice-rom.bit failed: not all outputs were created or valid
Use --verbose_failures to see the command lines of failed build steps.
INFO: Elapsed time: 3251.908s, Critical Path: 242.55s
INFO: 8657 processes: 23127 action cache hit, 4436 internal, 4132 linux-sandbox, 89 local.
ERROR: Build did NOT complete successfully`
```

Reproduce the earlgrey_1.0.0 build with Vivado Lab Edition and inspect hw/bitstream/universal/BUILD at line 29. Start with the reported update_mem command and the memories.mmi and bitstream inputs; done means the SpliceBitstream step creates splice-rom.bit without the xc7k410t unsupported-device error.

Written by the indexing model from the issue text.