[test-triage] [rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0]

Hierarchy of regression failure

Chip Level

Failure Description

While running the empty test, the corrupted ROM test is failing during the nightly regression. Does anyone know how to fix this issue? Is there any tag or branch where this issue has been fixed? I can see that this issue was already raised earlier, but the branch has been removed.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
  • Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.

    • 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.105961135603861122205902107047993930602370544893322851040531127566260543691420
      Line 523, in log /opentitan/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log

        UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Steps to Reproduce

1. ./util/dvsim/dvsim.py ./hw/top_earlgrey/dv/chip_sim_cfg.hjson -i rom_e2e_sigverify_always --tool vcs -r 1
2. ./util/dvsim/dvsim.py ./hw/top_earlgrey/dv/chip_sim_cfg.hjson -i rom_e2e_boot_policy_valid --tool vcs -r 1

Tests with similar or related failures

1. rom_e2e_boot_policy_valid_a_bad_b_good_dev
2. rom_e2e_boot_policy_valid_a_bad_b_good_prod
3. rom_e2e_boot_policy_valid_a_bad_b_good_prod_end
4. rom_e2e_boot_policy_valid_a_bad_b_good_rma
5. rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0
6. rom_e2e_boot_policy_valid_a_good_b_bad_dev
7. rom_e2e_boot_policy_valid_a_good_b_bad_prod
8. rom_e2e_boot_policy_valid_a_good_b_bad_prod_end
9. rom_e2e_boot_policy_valid_a_good_b_bad_rma
10. rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0
11. rom_e2e_sigverify_always_a_bad_b_bad_dev
12. rom_e2e_sigverify_always_a_bad_b_bad_prod
13. rom_e2e_sigverify_always_a_bad_b_bad_prod_end
14. rom_e2e_sigverify_always_a_bad_b_bad_rma
15. rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0
16. rom_e2e_sigverify_always_a_bad_b_nothing_dev
17. rom_e2e_sigverify_always_a_bad_b_nothing_prod
18. rom_e2e_sigverify_always_a_bad_b_nothing_prod_end
19. rom_e2e_sigverify_always_a_bad_b_nothing_rma
20. rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0
21. rom_e2e_sigverify_always_a_nothing_b_bad_dev
22. rom_e2e_sigverify_always_a_nothing_b_bad_prod
23. rom_e2e_sigverify_always_a_nothing_b_bad_prod_end
24. rom_e2e_sigverify_always_a_nothing_b_bad_rma
25. rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0

Start by running the two dvsim commands in the issue and inspect the failure at mem_bkdr_util.sv:597, especially why empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem cannot be opened. Compare the listed related ROM tests and their generated files. Done means the missing-file cause is identified and the affected regression tests no longer fail.