lowRISC / lowRISC/opentitan

[chip-test] [chip_sw_alert_handler_lpg_sleep_mode_alerts] Error:[CHECK-fail: testing_utilities != ((void*)0)]

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Component:ChipLevelTest
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Description

### Test point name

[chip_sw_alert_handler_lpg_sleep_mode_alerts][https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html?highlight=chip_sw_alert_handler_lpg_sleep_mode_alerts#stage-v2-testpoints]

### Host side component

None

### OpenTitanTool infrastructure implemented

None

### Silicon Validation (SiVal)

None

### Emulation Targets

- [x] None
- [ ] CW310
- [ ] Hyperdebug + CW310

### Contact person

_No response_

### Checklist

Hi,

Could anyone provide insight into the errors encountered while running the **chip_sw_alert_handler_lpg_sleep_mode_alerts** and **chip_sw_alert_test** tests, as detailed below?

**TEST: [chip_sw_alert_handler_lpg_sleep_mode_alerts]**
* `UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)` has 1 failure:
* Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failure:
* 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.26670354696938982250665142862621597651077224384348666175391166908794773147898
Line 957, /opentitan/scratch/os_regression/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 2988.734152 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2988.734152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

**TEST: [chip_sw_alert_test]**
* `UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!` has 1 failure:
* Test chip_sw_alert_test has 1 failure:
* 0.chip_sw_alert_test.112125334164043639926466574470850813346909221412536420894509003312000215511925
Line 1487, in log /opentitan/scratch/os_regression/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_test/latest/run.log
UVM_ERROR @ 2379.893916 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
UVM_INFO @ 2379.893916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Can anyone explain why these errors are occurring and how to resolve this issue?

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First steps

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  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start by reviewing the two failing run.log entries and the referenced locations in sw/device/lib/testing/ret_sram_testutils.c and hw/top_earlgrey/sw/autogen/tests/alert_test.c. Compare those failures with the test entry points and the sw_logger_if.sv reporting context. Done means identifying why each check fails and documenting or implementing a verified resolution for both tests.

Written by the indexing model from the issue text.

Assessment

Tech stack
c
Domain
embedded-iot, testing-qa
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
30/100

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