lowRISC / lowRISC/opentitan

[ac_range_check] V1+V2 Review & Signoff

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@rswarbrick is already working on this.

Since Aug 1, 2025.

IP:ac_range_check
Dominant language
SystemVerilog
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Description

Verification specification checks / updates

DV environment checks

Test suite / results checks

  • SIM_SMOKE_TEST_PASSING
  • SIM_CSR_MEM_TEST_SUITE_PASSING
  • SIM_SMOKE_REGRESSION_SETUP
  • SIM_NIGHTLY_REGRESSION_SETUP plus TB_LINT_SETUP
  • SIM_ALL_TESTS_PASSING
  • SIM_NIGHTLY_REGRESSION_V2
  • SIM_CODE_COVERAGE_V2
  • SIM_FUNCTIONAL_COVERAGE_V2

Tools checks

  • SIM_ALT_TOOL_SETUP

Issues checks

  • NO_HIGH_PRIORITY_ISSUES_PENDING
  • ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED

Security checks

Any non-standard security countermeasures are excluded from this signoff, hence SEC_CM_PLANNED is waived.

Various checks

The following items are also part of the V1 signoff checklist.
They are explicitly included in tasks listed above and are not tracked separately; their current status is visible in the checklist document for this IP:

  • DV_DOC_DRAFT_COMPLETED (done as part of DV_DOC_COMPLETED)
  • TB_TOP_CREATED (done as part of DV_DOC_COMPLETED)
  • PRELIMINARY_ASSERTION_CHECKS_ADDED (done as part of DV_DOC_COMPLETED)
  • SIM_TB_ENV_CREATED (done as part of DV_DOC_COMPLETED)
  • SIM_RAL_MODEL_GEN_AUTOMATED (done as part of DV_DOC_COMPLETED)
  • CSR_CHECK_GEN_AUTOMATED (done as part of DV_DOC_COMPLETED)
  • SIM_COVERAGE_MODEL_ADDED (done as part of DV_DOC_COMPLETED)
  • TB_LINT_SETUP (done as part of SIM_NIGHTLY_REGRESSION_SETUP)
  • STD_TEST_CATEGORIES_PLANNED (done as part of TESTPLAN_REVIEWED)
  • V2_CHECKLIST_SCOPED (done as part of TESTPLAN_REVIEWED)

The following item does not apply to this IP, as only the one configuration currently instantiated in Darjeeling gets verified:

  • TB_GEN_AUTOMATED

The following item does not apply to this IP, as it has no pre-verified submodules.

  • PRE_VERIFIED_SUB_MODULES_V1
  • PRE_VERIFIED_SUB_MODULES_V2

The following items are also part of the V2 signoff checklist.
They are explicitly included in tasks listed above or not necessary, and they are not tracked separately.
Their current status is visible in the checklist document for this IP:

  • DESIGN_DELTAS_CAPTURED_V2 (no design deltas since initial DV document and testplan review, which falls together with this review)

Contributor guide

Open the contributing guide

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Assessment

This issue has not been assessed yet.

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