[ac_range_check] DV environment checks (V2 subtask)
@rswarbrick is already working on this.
Since Aug 1, 2025.
- Dominant language
- SystemVerilog
- Stars
- 3.6k
- Forks
- 1.1k
- Avg merge
- 2d 22h
- Merged PRs (30d)
- 141
Description
- [ ] FUNCTIONAL_COVERAGE_IMPLEMENTED
Once TESTPLAN_COMPLETED and TESTPLAN_REVIEWED are done, review the DV code to check that functional coverage is completely implemented.
Confirm completeness or list all missing cover points / cover groups.
- [ ] ALL_INTERFACES_EXERCISED
Once PORT_FROZEN is complete, review the DV code to check that all ports of the DUT are connected and exercised.
Confirm completeness or list all ports missing connection / exercising.
- [ ] ALL_ASSERTION_CHECKS_ADDED
Once TESTPLAN_COMPLETED and TESTPLAN_REVIEWED are done, review the DV code to check that all planned assertions have been written and enabled.
Confirm completeness or list all missing assertions.
- [ ] SIM_TB_ENV_COMPLETED
Once TESTPLAN_COMPLETED and TESTPLAN_REVIEWED are done, review the DV code to check that all checks in the scoreboard have been implemented and enabled.
Confirm completeness or list all checks.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.