[ac_range_check] DV_DOC_COMPLETED (V2 item)
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@martin-velay is already working on this.
Since Aug 1, 2025.
IP:ac_range_check
- Dominant language
- SystemVerilog
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Description
Check and fix or confirm that the DV document is fully complete.
This task also includes the following V1 checklist items:
- DV_DOC_DRAFT_COMPLETED
- TB_TOP_CREATED
- PRELIMINARY_ASSERTION_CHECKS_ADDED
- SIM_TB_ENV_CREATED
- SIM_RAL_MODEL_GEN_AUTOMATED
- CSR_CHECK_GEN_AUTOMATED
- SIM_COVERAGE_MODEL_ADDED
The idea is that the DV code needs to be looked through to ensure that the DV document is up to date, and those items can be completed on the same pass.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.