lowRISC / lowRISC/opentitan

[racl_ctrl] DESIGN_SPEC_REVIEWED (V1 item)

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#27,759 1 comment 0 reactions 1 assignee Claimed by @rswarbrick View on GitHub
IP:racl_ctrl
Dominant language
SystemVerilog
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Description

Review the design / micro-architecture specification (once the SPEC_COMPLETE D1 item is done) and sign it off from a DV perspective.

Contributor guide

Open the contributing guide

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