[component] Incomplete Structure Literal Causes Vivado Error in `spid_common.sv`

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### Description

**File:** `hw/ip/spi_device/pre_dv/tb/spid_common.sv`

While working with this file, I encountered a Vivado compilation error due to an incomplete structure literal. The error reported is:

```
ERROR: [VRFC 10-9103] incomplete structure literal; no value is specified for field 'read_pipeline_mode'
```

This occurs during the initialization of a structure literal similar to the following:

```systemverilog
// 27: WRDI
'{
valid: 1'b 1,
opcode: 8'h 04,
addr_mode: AddrDisabled,
addr_swap_en: 1'b 0,
mbyte_en: 1'b 0,
dummy_en: 1'b 0,
dummy_size: '0,
payload_en: 4'b 0001, // MISO
payload_dir: PayloadIn,
payload_swap_en: 1'b 0,
upload: 1'b 0,
busy: 1'b 0
}
```

The field `read_pipeline_mode` is declared in the struct definition but is omitted from the initialization, which causes the Vivado simulator to report an error.

### Why this should be fixed

According to the IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language (IEEE Std 1800-2023), page 264 §10.9.2 *Structure assignment patterns*:

> "Every member shall be covered by one of these rules."

This means that when using a structure literal with named member assignments, **all members** of the structure must be explicitly assigned, either via `member: value`, `type: value`, or `default: value`. Omitting any field results in an incomplete structure, which is not permitted by the standard and explains the compiler error.

Open hw/ip/spi_device/pre_dv/tb/spid_common.sv and compare the structure definition with the literal around the WRDI entry. Determine the appropriate value for read_pipeline_mode from the surrounding declarations or literals, add the missing member assignment, and rerun the Vivado compilation to confirm the incomplete-structure error is gone.

Written by the indexing model from the issue text.