Porting TLTs on Xcelium
- Dominant language
- SystemVerilog
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Description
This issue lists the tests completely/partially passing on VCS and failing on Xcelium.
The list below is "dynamic" and will be updated as things get fixed. It's intended to be a list of buckets that group together common failure modes. In all cases, these are tests that pass for all seeds on VCS but fail for all seeds on Xcelium.
# Manual buckets
## `$assertoff` hierarchy
Tracked as #27750.
- chip_sw_pwrmgr_sleep_power_glitch_reset
- chip_sw_pwrmgr_deep_sleep_power_glitch_reset
- chip_sw_pwrmgr_random_sleep_power_glitch_reset
- chip_sw_pwrmgr_main_power_glitch_reset
```
xmsim: *E,ASRTST (scratch/HEAD/chip_earlgrey_asic-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2824490 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
UVM_ERROR @ 2824.490000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
UVM_INFO @ 2824.490000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
```
# Uncategorised
## `rom_e2e_shutdown_output`
```
UVM_ERROR @ 6933.414503 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
BF" == "OpenTitan:4001-0002-01x0d
```
## `rom_e2e_shutdown_exception_c`
```
UVM_ERROR @ 14247.224201 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
BF" == "OpenTitan:4001-0002-01x0d
```
## `rom_e2e_jtag_debug_rma`
```
UVM_ERROR @ 3229.736200 us: (chip_sw_rom_e2e_jtag_debug_vseq.sv:94) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_jtag_debug_vseq] Check failed (breakpoints.size() == 3)
```
Contributor guide
Research direction
Start with the listed failing tests and reproduce their Xcelium failures, beginning with the assertion location in pwrmgr_slow_fsm.sv:362 and the checks in chip_sw_rom_e2e_base_vseq.sv:37 and chip_sw_rom_e2e_jtag_debug_vseq.sv:94. Compare each result with VCS behavior and group the failures into actionable buckets; done means the listed tests pass on Xcelium or have their remaining failure modes tracked.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing-qa
- Issue type
- Bug
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100