[sival,ci] SiVal-only tests must specify some DV `stage` property

### Description

In our testplans, there are some tests that only have Bazel SW targets and do not have corresponding DV targets. The current JSON testplan schema used for validation in CI linting does not allow a `NA`/`None` value for the DV stage, whereas it does for the `si_stage`, meaning any tests that are not intended to have DV targets must still specify a DV stage. Examples of tests that do this include for example [some of the I2C testpoints](https://github.com/lowRISC/opentitan/blob/a30d495ede4f767ab7f98bb1dd196ed4a82758b0/hw/top_earlgrey/data/ip/chip_i2c_testplan.hjson#L104-L173).

We should ideally change the Schema to allow for an `NA` `stage` value, and go through and mark existing tests that should not have DV targets with this `stage`.

Start with the JSON testplan schema used for CI linting and inspect the linked I2C testplan examples. Confirm how `si_stage` accepts `NA`/`None`, then define the corresponding `NA` handling for DV stages and identify existing tests without DV targets that need updating; done means the schema accepts them and CI validation passes.

Written by the indexing model from the issue text.