lowRISC / lowRISC/opentitan

[rv_dm/dv] Verify `lc_hw_debug_clr_i`

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#27,435 0 comments 0 reactions 0 assignees View on GitHub
Component:DV IP:rv_dm
Dominant language
SystemVerilog
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Forks
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Avg merge
2d 22h
Merged PRs (30d)
141

Description

PR #27331 added functionality to clear the `strap_hw_debug_en_q` flop in `rv_dm_dmi_gate` when `lc_ctrl` disables HW Debug without a reset. This only affects instances of `rv_dm` with the `UseDmiParameter` set to `1`.

This new functionality needs to be verified (functional as well as security countermeasure verification). In block-level DV, this is the `use_dmi_interface` variant configured in `rv_dm_use_dmi_interface_sim_cfg.hjson`.

Contributor guide

Open the contributing guide

Research direction

Start by reading PR #27331 and the block-level DV configuration in rv_dm_use_dmi_interface_sim_cfg.hjson, which selects the relevant use_dmi_interface variant. Identify the verification entry points for rv_dm_dmi_gate and check that disabling HW Debug through lc_ctrl clears strap_hw_debug_en_q without reset. Done means both functional behavior and the security countermeasure are verified.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, security, testing-qa
Issue type
Feature
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
42/100

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