[dv,fusesoc-upgrade] Provide a mechanism to assign integrator DFT ports

@hcallahan-lowrisc is already working on this.

Since Jun 11, 2025.

### Description

For example in the sram_ctrl testbench, we added code downstream to properly set the DFT vector when selecting the foundry prim library:

```systemverilog
always_comb begin
ram_cfg = '0;

if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplIntegrator) begin : gen_impl_integrator
// Integrator RAM config
ram_cfg.field1 = 3'h5;
ram_cfg.field2 = 4'h4;
ram_cfg.field3 = 1'h1;
end
end
```

When not selecting the foundry lib, i.e., when compiling to verilator a default `'0` was passed.

With the recent fuseoc upgrade and the deprecation of `prim_pkg`, this is going to be removed. What would be the alternative to solve this problem?

/cc @a-will @andreaskurth