lowRISC / lowRISC/opentitan

[top_darjeeling] unresolved parameter "Addrcheck"

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Component:Darjeeling
Dominant language
SystemVerilog
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Description

### desc

![Image](https://github.com/user-attachments/assets/6db2932d-1792-4f57-abf5-e8a488b210ae)

./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_uart_tx_rx,run with this command,report issue like the picture

Contributor guide

Open the contributing guide

Research direction

Start with util/dvsim/dvsim.py and the hw/top_earlgrey/dv/chip_sim_cfg.hjson configuration used by the reported command. Reproduce the chip_sw_uart_tx_rx run and inspect how the unresolved "Addrcheck" parameter is parsed or reported; done means identifying the source of the error and confirming the command runs without it.

Written by the indexing model from the issue text.

Assessment

Tech stack
python
Domain
testing
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
35/100

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