lowRISC / lowRISC/opentitan

[multi_top,clock] Make dv_lib clock frequencies compatible with multi-top

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@alees24 is already working on this.

Since Apr 30, 2025.

Component:DV Component:MultiTop
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SystemVerilog
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Description

Description

The dv_lib clock frequencies for block-level sims are randomized for earlgrey using https://github.com/lowRISC/opentitan/blob/master/hw/dv/sv/dv_utils/dv_macros.svh#L609. This is okay for simple blocks but can cause trouble for blocks with multiple clocks since the clock ratios can be too far off admissible values. One example is clkmgr for darjeeling, where this makes the "clk" configured via dv_lib to be about the same rate as the AON clock. A similar setting that is problematic for darjeeling is the special setting of the AON clock frequency: this was helpful for earlgrey but will be detrimental for darjeeling.

I think this may explain the failures of clkmgr_frequency_timeout for darjeeling: the clkmgr clk_i is running too slow so the alert arrives much later than the test expects it, but at least it arrives in the case I am examining.

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