[chip-test]kmac_error_conditions_test failing in silicon regression tests
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@moidx is already working on this.
Since Apr 16, 2025.
Component:ChipLevelTest
Component:SiliconValidation
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- SystemVerilog
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Description
Test point name
[chip_sw_kmac_error_conditions]https://github.com/lowRISC/opentitan/blob/master/sw/device/tests/kmac_error_conditions_test.c
Host side component
None
OpenTitanTool infrastructure implemented
None
Silicon Validation (SiVal)
Yes
Emulation Targets
- None
- CW310
- Hyperdebug + CW310
Contact person
rprakas-gsc
Checklist
Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.
- Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
- Device-side (C) component developed
- Bazel build rules developed
- Host-side component developed
- HJSON test plan updated with test name (so it shows up in the dashboard)
- Test added to dvsim nightly regression (and passing at time of checking)
- For SiVal test cases, test is running relevant FPGA or silicon regression
This test is failing in silicon nightly regression - with the following error message
FAULT: Store Access Fault. MCAUSE=00000007 MEPC=20011bd4 MTVAL=00000018?
Contributor guide
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Assessment
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