lowRISC / lowRISC/opentitan

[chip-test] Store access fault error in kmac_error_conditions_test

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@moidx is already working on this.

Since Apr 8, 2025.

Component:ChipLevelTest Component:SiliconValidation
Dominant language
SystemVerilog
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Description

Test point name

chip_sw_kmac_error_conditions

Host side component

None

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets
  • None
  • CW310
  • Hyperdebug + CW310
Contact person

rprakas-gsc

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • HJSON test plan updated with test name (so it shows up in the dashboard)
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression

Here is the test output log from nightly regression runs

I00014 kmac_error_conditions_test.c:622] Testing ErrSwIssuedCmdInAppActive error.
===== Exception Frame @ 1001fe88 =====
 mepc=20011bd6   ra=20011bb0   t0=1001fe4b   t1=00000006
   t2=00000036   s0=2001bad2   s1=200187c0   a0=10002070
   a1=00000000   a2=00002030   a3=41120000   a4=2001b18f
   a5=2001875d   a6=2001b284   a7=20016986   s2=1001fefc
   s3=00000480   s4=00000400   s5=00008430   s6=10000046
   s7=20010000   s8=0000c520   s9=00000739  s10=00000000
  s11=00000000   t3=fffffffd   t4=0000002c   t5=9076b573
   t6=20018a78 msts=00001800
===== Call Stack =====
    20011c86
    20014cbe
    20014c1e
    20010548
    20010548
    200104c4
E00015 ottf_isrs.c:99] FAULT: Store Access Fault. MCAUSE=00000007 MEPC=20011bd4 MTVAL=00000018
[2025-04-07T17:02:51Z INFO  opentitantool::command::console] ExitFailure("FAULT: Store Access Fault. MCAUSE=00000007 MEPC=20011bd4 MTVAL=00000018\r\n")

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