[test-triage,earlgrey] chip_sw_ast_clk_rst_inputs
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Description
### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ 19266.254833 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
### Steps to Reproduce
- GitHub Revision: 950d8cda3209783a1abab34cf3444d686866a1f6
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_ast_clk_rst_inputs --fixed-seed 1
### Tests with similar or related failures
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Research direction
Reproduce the regression with ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_ast_clk_rst_inputs --fixed-seed 1 at revision 950d8cda3209783a1abab34cf3444d686866a1f6. Start with sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128 and the sw_logger_if.sv:526 failure, then determine why the recovery alert is not observed correctly; done means the check passes.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100