[test-triage,earlgrey] chip_sw_power_sleep_load
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Component:TestTriage
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- SystemVerilog
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Description
Hierarchy of regression failure
Chip Level
Failure Description
UVM_ERROR @ 3299.126000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
Steps to Reproduce
- GitHub Revision: 950d8cda3209783a1abab34cf3444d686866a1f6
- dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_power_sleep_load --fixed-seed 1
Tests with similar or related failures
No response
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by running the provided dvsim command at revision 950d8cda3209783a1abab34cf3444d686866a1f6, then inspect chip_sw_power_sleep_load_vseq.sv at line 114. Investigate why PWMCH3 reports a clock period of 2 instead of 32, and consider the issue resolved when this regression no longer produces the reported UVM error.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100