lowRISC / lowRISC/opentitan

[Multitiop, test] chip_sw_uart_tx_rx

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Component:ChipLevelTest
Dominant language
SystemVerilog
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Description

### Description

Tests should not depend on earlgrey constants. Try removing #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" and see what doesn't compile.
Replace any dif_uart_init with dif_uart_init_from_dt to avoid TOP_EARLGREY_UART_BASE_ADDR.
Add //hw/top:dt to deps to get all device table libraries.
Use bazel build //hw/top:dt_api_hdr and bazel build //hw/top:dt_uart_hdr to see the autogenerated DT headers. The _src suffix shows the C files.
Grep for kClockFreq.*. These are top-specific but don't come from a top_earlgrey header. Replace with dt_clock_frequency(...).
For ISRs: replace peripheral = with dt_plic_id_to_instance_id and compare to the DT instance using dt_uart_instance_id(dt__t).
Again for ISRs, convert the plic IRQ ID to a block-specific ID with dt_uart_irq_from_plic_id and switch on that.
The test chip_sw_uart_tx_rx should run and pass for Ealrgrey and Darjeeling.

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First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start with the chip_sw_uart_tx_rx test and remove its top_earlgrey.h dependency, then inspect the referenced dif_uart_init calls, clock-frequency uses, and ISR handling. Use //hw/top:dt dependencies and run the listed dt_api_hdr and dt_uart_hdr Bazel builds to inspect generated headers. Done means the test builds and passes for Earlgrey and Darjeeling without top-specific constants.

Written by the indexing model from the issue text.

Assessment

Tech stack
c
Domain
build-system, embedded-iot, testing-qa
Issue type
Refactor
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Clearly specified
Newbie friendliness
45/100

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