[test-triage, darjeeling] chip_sw_soc_proxy_external_alerts

### Hierarchy of regression failure

Chip Level

### Failure Description

```
* `UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect!` has 1 failures:
* Test chip_sw_soc_proxy_external_alerts has 1 failures.
* 0.chip_sw_soc_proxy_external_alerts.1\
Line 1519, in log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_soc_proxy_external_alerts/latest/run.log

UVM_ERROR @ 4857.156398 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
UVM_INFO @ 4857.156398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

```

### Steps to Reproduce

- GitHub Revision: master
```sh
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_sw_soc_proxy_external_alerts

```

### Tests with similar or related failures

- [ ] chip_sw_soc_proxy_external_alerts