[test-triage, darjeeling] chip_sw_rv_core_ibex_nmi_irq

### Hierarchy of regression failure

Chip Level

### Failure Description

```
* `UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired` has 1 failures:
* Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
* 0.chip_sw_rv_core_ibex_nmi_irq.1\
Line 1502, in log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

UVM_ERROR @ 4624.608476 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 4624.608476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
```

### Steps to Reproduce

- GitHub Revision: master
```sh
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_sw_rv_core_ibex_nmi_irq
```

### Tests with similar or related failures

- [ ] chip_sw_rv_core_ibex_nmi_irq

Reproduce chip_sw_rv_core_ibex_nmi_irq with the listed util/dvsim/dvsim.py command and inspect the failure in sw/device/tests/rv_core_ibex_nmi_irq_test.c:172 and the referenced run.log. Trace why the test times out waiting for nmi_fired; done means the regression no longer reports this timeout.

Written by the indexing model from the issue text.