[test-triage, darjeeling] chip_sw_rstmgr_cpu_info

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### Hierarchy of regression failure

Chip Level

### Failure Description

```
* `UVM_ERROR @ * us: (chip_sw_base_vseq.sv:375) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns` has 1 failures:
* Test chip_sw_rstmgr_cpu_info has 1 failures.
* 0.chip_sw_rstmgr_cpu_info.1\
Line 1515, in log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rstmgr_cpu_info/latest/run.log

UVM_ERROR @ 20019.388725 us: (chip_sw_base_vseq.sv:375) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

UVM_INFO @ 20019.388725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
```

### Steps to Reproduce

- GitHub Revision: master
```sh
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_sw_rstmgr_cpu_info

```

### Tests with similar or related failures

- [ ] chip_sw_rstmgr_cpu_info

Reproduce chip_sw_rstmgr_cpu_info with the supplied util/dvsim/dvsim.py command and inspect the referenced run.log, especially the timeout reported from chip_sw_base_vseq.sv:375. Trace why the test remains in SwTestStatusInTest and confirm that the regression no longer reports the timeout.

Written by the indexing model from the issue text.