[test-triage, darjeeling] chip_sw_rstmgr_alert_info
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Component:TestTriage
- Dominant language
- SystemVerilog
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Description
Hierarchy of regression failure
Chip Level
Failure Description
* `UVM_FATAL @ * us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info *` has 1 failures:
* Test chip_sw_rstmgr_alert_info has 1 failures.
* 0.chip_sw_rstmgr_alert_info.1\
Line 1513, in log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_FATAL @ 6202.761478 us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info 20
UVM_INFO @ 6202.761478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Steps to Reproduce
- GitHub Revision: master
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_sw_rstmgr_alert_info
Tests with similar or related failures
- chip_sw_rstmgr_alert_info
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by running the provided util/dvsim/dvsim.py command with hw/top_darjeeling/dv/chip_sim_cfg.hjson and xcelium, then inspect sw/device/tests/rstmgr_alert_info_test.c around line 859 and the reported run.log failure. Determine why chip_sw_rstmgr_alert_info reports unexpected reset info 20; done means the reproduced test no longer emits the UVM_FATAL failure.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- c
- Domain
- embedded-iot, testing-qa
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100