[test-triage, darjeeling] chip_sw_kmac_app_rom

### Hierarchy of regression failure

Chip Level

### Failure Description

```
* `UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode` has 1 failures:
* Test chip_sw_kmac_app_rom has 1 failures.
* 0.chip_sw_kmac_app_rom.1\
Line 1477, in log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_kmac_app_rom/latest/run.log

UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---

``

### Steps to Reproduce

- GitHub Revision: master
```sh
util/dvsim/dvsim.py hw/top_darjeeling/dv/chip_sim_cfg.hjson --tool xcelium -v m --fi 1 -i chip_sw_kmac_app_rom
```

### Tests with similar or related failures

- [ ] chip_sw_kmac_app_rom

Start by rerunning util/dvsim/dvsim.py with hw/top_darjeeling/dv/chip_sim_cfg.hjson, the xcelium tool, and chip_sw_kmac_app_rom. Inspect the resulting run.log and the missing kmac_app_rom_test_sim_dv.32.vmem reference around mem_bkdr_util.sv:563. Done means the regression completes without the file-open UVM_FATAL.

Written by the indexing model from the issue text.